1. Field of the Invention
The present invention relates to a liquid crystal display device, and specifically relates to a liquid crystal display device which samples and holds a positive video signal and a negative video signal separately in two hold capacitors in each pixel and then carries out AC drive of a liquid crystal display element by applying held voltages thereof alternately to a pixel electrode.
2. Description of the Related Art
In recent years, an LCOS (Liquid Crystal on Silicon) type liquid crystal display device has been used frequently for a projector apparatus and a projection TV as a central component for projecting an image. As this LCOS type liquid crystal display device, the present applicant previously proposed a liquid crystal display device which arranges pixels in a matrix at respective intersection parts of a plurality of sets of data lines (column signal lines), each set including two data lines, and a plurality of gate lines (row scan lines), samples and holds a positive video signal and a negative video signal separately in two hold capacitors in each of the pixels, and then carries out AC drive of a liquid crystal display element by applying held voltages thereof alternately to a pixel electrode (refer to Patent document 1 (Japanese Patent Laid-Open No. 2009-223289), for example).
FIG. 1 shows an example of an equivalent circuit diagram for a pixel of this liquid crystal display device. In FIG. 1, a pixel comprises pixel selection transistors Tr1 and Tr2 for writing a positive video signal and a negative video signal, respectively, two independent hold capacitors Cs1 and Cs2 holding video signal voltages of both polarities in parallel, respectively, transistors Tr3 to Tr7 and a liquid crystal display element LC. The liquid crystal display element LC has a well-known structure in which a liquid crystal layer (display medium) LCM is sandwiched between a pixel electrode PE and a common electrode CE which are disposed so as to face each other,
Further, the pixel selection transistors Tr1 and Tr2 and the switching transistors Tr5 and Tr6 are N-channel MOS field effect transistors (hereinafter called NMOS transistors), and the transistors Tr3, Tr4 and Tr7 are P-channel MOS field effect transistors (hereinafter called PMOS transistors). The transistors Tr3 and Tr7 and the transistors Tr4 and Tr7 are so-called source-follower buffers, respectively, and the transistors Tr3 and Tr4 are source-follower transistors and the transistor Tr7 is a transistor functioning as a constant current source load. The source-follower buffer of the MOS transistor has an almost infinitely large input resistance, and accumulated charge in each of the hold capacitors Cs1 and Cs2 is not leaked but held until the signal is newly written after one vertical scan period.
Further, a pixel part data line is configured with a set of two data lines, a positive data line Di+ and a negative data line Di−, for each pixel, and supplies video signals which are sampled by a data line drive circuit (not shown in the drawing) and have polarities different from each other. Drain terminals of the pixel selection transistors Tr1 and Tr2 are connected to the positive data line Di+ and the negative data line Di−, respectively, and respective gate terminals thereof for the same row are connected to a row scan line (gate line) Gj. Further, the constant current load transistors Tr7 are configured such that respective gates thereof in the same row pixels are connected to a common wiring B in the row direction and bias control of the constant current load is possible. Further, wirings S+ and S− are wirings for gate control signals and connected separately to gates of the transistors Tr5 and Tr6, respectively. Moreover, the row scan line Gj is connected commonly to the transistors Tr1 and Tr2 in the plurality of pixels in the same row.
Next, outline of AC drive control for this pixel will be explained with reference to a timing chart of FIG. 2. FIG. 2(A) shows a vertical synchronization signal VD which is a reference for vertical scan of a video signal, and FIG. 2(B) shows a load characteristic control signal of the wiring B which is applied to the gate of the transistor Tr7 in the pixel of FIG. 1. Further, FIG. 2(C) and FIG. 2(D) show signal waveforms of a gate control signal of the wiring S+ which is applied to the gate of the switching transistor Tr5 for transferring a positive side drive voltage in the above pixel and a gate control signal of the wiring S− which is applied to the gate of the switching transistor Tr6 for transferring a negative side drive voltage in the above pixel, respectively.
In FIG. 1, the positive side switching transistor Tr5 is turned on during a period when the gate control signal of the wiring S+ shown in FIG. 2(C) exhibits a high level, and when the load characteristic control signal supplied to the wiring B during this period is caused to exhibit a low level as shown in FIG. 2(B), the source-follower buffer becomes active and a pixel electrode PE node is charged to have a positive video signal level. When the potential of the pixel electrode PE has a potential of a fully charged state, the load characteristic control signal of the wiring B is caused to have a high level and also the gate control signal of the wiring S+ is switched to exhibit a low level at this timing, and then the pixel electrode PE comes to have a floating state and a positive drive voltage is held in liquid crystal capacitance.
On the other hand, the negative side switching transistor TR6 is turned on during a period when the gate control signal of the wiring S− shown in FIG. 2(D) exhibits a high level, when the load characteristic control signal supplied to the wiring B is caused to exhibit a low level during this period as shown in FIG. 2(B), the source-follower buffer becomes active and the pixel electrode PE node is charged to have a negative video signal level. When the pixel electrode PE is charged to have a fully charged state, the load characteristic control signal of the wiring B is caused to have a high level and also the gate control signal of the wiring S− is switched to exhibit a low level at this timing, and then the pixel electrode PE comes to have a floating state and a negative drive voltage is held in the liquid crystal capacitance.
Next, in synchronization with the alternative switching of the above switching transistors Tr5 and Tr6, the transistor Tr7 is caused to be active intermittently by the load characteristic control signal of the wiring B, and, by the repetition of the above actions, a drive voltage VPE, which is caused to change alternately by the positive and negative video signals, is applied to the pixel electrode PE of the liquid crystal display element LC as shown in FIG. 2(E). The pixel shown in FIG. 1 is configured not to transfer a held charge directly to the pixel electrode PE but to supply a voltage via the source-follower buffer, and thereby, even when charge and discharge is performed repeatedly between the negative and positive polarities, there is not a problem of charge neutralization and it is possible to realize a drive without voltage level attenuation.
Further, Vcom shown in FIG. 2(F) shows a voltage to be applied to a common electrode CE formed on an opposite substrate of the liquid crystal display device. A substantial AC drive voltage applied to the liquid crystal layer LCM is a differential voltage between the voltage Vcom applied to this common electrode CE and the voltage applied to the pixel electrode PE. As shown in FIG. 2(F), the voltage Vcom applied to the common electrode CE is inverted against a reference level which is approximately equal to an inversion reference level Vc of the pixel electrode potential in synchronization with the switching of the pixel polarity.
Further, the positive and negative video signal voltages sampled and held in the hold capacitors Cs1 and Cs2 are read out via the source-follower transistors Tr3 and Tr4 each having a high input resistance, respectively, and, as shown in FIGS. 2(C) and 2(D), selected alternately by the switching transistors Tr5 and Tr6 which are turned on by the gate control signal supplied alternately to the wirings S+ and S−, respectively, and then applied to the pixel electrode PE as the drive voltage VPE shown in FIG. 2(E) which is inverted between a positive polarity and a negative polarity. In this pixel shown in FIG. 1, the positive and negative video signal voltages are written in the hold capacitors Cs1 and Cs2, respectively, once in one vertical scan period (one frame), and then the video signal voltages can be read out from the respective hold capacitors Cs1 and Cs2 infinitely often during the one frame period until the video signal voltages of the next frame are held, and the liquid crystal display element LC can be driven in an AC mode by the alternate switching of the transistors Tr5 and Tr6. Accordingly, in the pixel shown in FIG. 1, the liquid crystal display element LC can be driven in the AC mode at a high frequency without a restriction in a vertical scan frequency independently from a write cycle of the video signal.
This AC drive frequency does not depend on the vertical scan frequency and can be set freely according to an inversion control period in a pixel circuit. For example, the vertical scan frequency is assumed to be 60 Hz which is used for a typical TV video signal and a frame is assumed to be configured with vertical period scan lines of 1,125 lines for the full High Vision. When the polarity switching of the pixel circuit is performed in cycles of approximately 15 lines, the AC drive frequency of the liquid crystal display element becomes 2.25 kHz (=60 (Hz)×1,125÷(15×2)) and the liquid crystal drive frequency can be significantly increased compared with a conventional liquid crystal display device. Accordingly, it is possible to prevent image sticking compared with a case in which the liquid crystal display element has a low AC drive frequency, and it becomes possible to significantly improve reliability and safety, display quality degradation such as a smear.
Note that the constant current load transistor Tr7 of the source-follower buffer is not always caused to be active in consideration of current consumption in the liquid crystal display device and controlled so as to be active only a limited period within the conduction period of the switching transistor Tr5 of Tr6. For example, even when constant source-follower circuit current is a small current of 1 μA for one pixel circuit, there is a problem that the current causes a large current consumption in a condition in which all the pixels of the liquid crystal display device consume the current constantly, and the current consumption is estimated to reach even 2 A in a liquid crystal display device having 2 million pixels for the full High Vision, for example.
Accordingly, in the pixel shown in FIG. 1, the low level period of the load characteristic control signal B which provides a gate bias for the constant current load transistor Tr7 is limited only to a transition period of the pixel voltage polarity switching period, and the load characteristic control signal B is caused to exhibit the high level immediately after the pixel electrode voltage VPE has been charged or discharged to a target level, to terminate the current of the source-follower buffer. Accordingly, despite the configuration of providing the buffers for all the pixels, it is possible to suppress substantial current consumption to a small value.
In the above conventional liquid crystal display device, as shown in FIG. 1, Tr1, Tr2, Tr5, and Tr6 are NMOS transistors and Tr3, Tr4, and Tr7 are PMOS transistors. Accordingly, the source-follower circuit using the PMOS transistors Tr3 and Tr4 is an amplifier having a gain of 0.87 and cannot be used for a high input voltage at which the output voltage to input voltage characteristic becomes nonlinear.
Further, in the above conventional liquid crystal display device, when a power supply voltage VDD is set to 5.5 V, as shown by the reference numeral IV in FIG. 8, a data line D+ and D− input voltage range of 0 V to 4.0 V is a linear range for outputting a voltage from 1.9 V to 4.8 V to the pixel electrode PE, but the output voltage curve starts to bend at an input voltage of 4.4 V. Since the linear range needs to be used for a dynamic range of the voltage to be applied to the liquid crystal display element LC, the dynamic range width of each pixel in the conventional liquid crystal display device becomes 2.9 V, that is, from 1.9 V to 4.8 V, for an input voltage of 0 V to 4.0 V. On the other hand, a voltage range to be applied to the liquid crystal display element LC needs to be approximately 3.8 V, and a narrower applied voltage range of the liquid crystal display element LC invites degradation of contrast and brightness. Accordingly, the conventional liquid crystal display device has a problem that the linear range of the source-follower output should be expanded.